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[ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)

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视频 2022-12-1 15:48 2024-11-15 00:27 199 2.91 GB 15
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文件列表
  1. ~Get Your Files Here !/1. Introduction/1. Introduction to CAD tools.mp4145.36MB
  2. ~Get Your Files Here !/10. VHDL parallel load counters and bus design/1. Parallel Load counters and bus design.mp4155.91MB
  3. ~Get Your Files Here !/11. VHDL code of the bus design with SWAP operation/1. VHDL code of the bus design with SWAP operation.mp4227.82MB
  4. ~Get Your Files Here !/12. Processor Design and its VHDL/1. Simple Processor Design and its VHDL.mp4466.35MB
  5. ~Get Your Files Here !/13. Modelsim/2. Modelsim Tutorial 1.mp4128.39MB
  6. ~Get Your Files Here !/13. Modelsim/3. Modelsim Tutorial 2.mp4189.48MB
  7. ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/1. Numbers Representations.mp488.86MB
  8. ~Get Your Files Here !/2. Numbers Representations & LUTs, PLDs, FPGA/2. LUTs, PLDs, FPGA.mp4111.15MB
  9. ~Get Your Files Here !/3. Half Adders, Full Adders, RCA, CLA/1. HA FA RCA CLA.mp4200.13MB
  10. ~Get Your Files Here !/4. VHDL Adders Multiplier Narrated/1. VHDL for adders, Multiplier.mp4293.82MB
  11. ~Get Your Files Here !/5. Multiplexers and Shannon Expansion/1. Multiplexers and Shannon Expansion.mp4308.1MB
  12. ~Get Your Files Here !/6. Decoders Arithmetic Comparator Selected signal assignment/1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4190.21MB
  13. ~Get Your Files Here !/7. Conditional statement generate statement/1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4196.28MB
  14. ~Get Your Files Here !/8. latches flipflops shift and parallel access registers/1. Latches, FlipFlops, parallel access and shift registers.mp4116.4MB
  15. ~Get Your Files Here !/9. VHDL gated latches flipflops, registers and counter/1. VHDL for Latches, FlipFlops, registers and counters.mp4158.36MB
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